module my_change(
  input   wire         clk         ,
  input   wire         rst_n       ,
  input   wire         din         ,
  (*mark_debug ="true"*)output  wire         convst      ,
  (*mark_debug ="true"*)output  wire         sclk_adc    ,
  (*mark_debug ="true"*)output  wire         sclk_dac    ,
  (*mark_debug ="true"*)output  wire         mosi        ,
  (*mark_debug ="true"*)output  wire         SYNC,
  (*mark_debug ="true"*)output  reg          dout
);
   reg             busy;
   reg             rd_ready;
   reg     [15:0]  tx_data;
   reg             tx_exec;  
  reg             rd_exec;
   reg     [7:0]   clk_cnt;
   reg             tx_ready_shift_reg1;
   reg             tx_ready_shift_reg2;   
   reg             rd_ready_shift_reg1;   
   reg             rd_ready_shift_reg2;      
   reg             tx_ready_co;
   reg             rd_ready_co;
    reg     [8:0]  cnt; 
   wire    [15:0]  rd_data;
   wire            busy_dac;
    wire            busy_adc;  
   wire            tx_ready;   
    wire            update;
    wire            working;
    wire    [15:0]  filter_out;    
always_ff@(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        dout<=1'b1;
        tx_ready_shift_reg1<=1'b0;
        tx_ready_shift_reg2<=1'b0;
        rd_ready_shift_reg1<=1'b0;
        rd_ready_shift_reg2<=1'b0;
        tx_ready_co<=1'b0;
        rd_ready_co<=1'b0;
    end
    else begin
        tx_ready_shift_reg2<=tx_ready_shift_reg1;
        tx_ready_shift_reg1<=tx_ready;
        rd_ready_shift_reg2<=rd_ready_shift_reg1;
        rd_ready_shift_reg1<=rd_ready;
        if(rd_ready_shift_reg2==0&&rd_ready_shift_reg1==1)
            rd_ready_co<=1'b1;
        else
            rd_ready_co<=1'b0;
        if(tx_ready_shift_reg2==0&&tx_ready_shift_reg1==1)
            tx_ready_co<=1'b1;
        else
            tx_ready_co<=1'b0;
    end
end

always_ff@(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
    rd_exec<=1'b0;
    tx_exec<=1'b0;    
    tx_data<=16'b0;
    end
    else begin
        if(update)begin
            rd_exec<=1'b1;
            tx_data<=filter_out[15:4]+16'H1000;
            //tx_data<=rd_data[15:4]+16'o1000;
            tx_exec<=1'b1;
        end
        else
        begin
            tx_exec<=1'b0;
            rd_exec<=1'b0;
        end
    end
end

Counter #(400) u_Counter (.clk(clk), .rst_n(rst_n), .en( 1'b1),.cnt(cnt),.co(update));


ads8865_driver u_ads8865_driver(
    .clk        (clk     ),
    .rst_n      (rst_n   ),
    .rd_exec    (rd_exec ),
    .din        (din     ),
    .convst     (convst  ),
    .sclk       (sclk_adc),
    .rd_data    (rd_data ),
    .rd_ready   (rd_ready),
    .busy       (busy_adc)
);

dac7881_drive u_dac7881_drive
(
    .clk        (clk     ),
    .rst_n      (rst_n   ),
    .tx_exec    (tx_exec ),
    .tx_data    (tx_data ),
    .tx_ready   (tx_ready),
    .SYNC       (SYNC    ),
    .busy       (busy_dac),
    .sclk       (sclk_dac),
    .mosi       (mosi    )
);
    IIR #(16, 4, 5, '{ 
0.999656101597113488921308999124448746443,
0.999656101597113488921308999124448746443, 
0.999101409695275166633621211076388135552,
0.999101409695275166633621211076388135552,
0.998889779817044631826661316154059022665}, // GAIN
'{  '{ 1, -1.999015586917585407533692887227516621351,  1       },              
    '{ 1, -1.999015586917585407533692887227516621351,  1       },              
    '{ 1, -1.999015586917585407533692887227516621351,  1       },
    '{ 1, -1.999015586917585407533692887227516621351,  1       },
    '{ 1, -1.999015586917585407533692887227516621351,  1       }
    },          
'{  '{    -1.998237576320943897911774911335669457912,   0.999290213970775997864848250173963606358},               
    '{    -1.998416449648296788765833298384677618742,   0.999336426916597408975917460338678210974},               
    '{    -1.997140533460913136565295644686557352543,   0.998165874740341796389486717089312151074}, 
    '{    -1.997297197449154460002773703308776021004,   0.998240618265740509151839887636015191674},
    '{    -1.996796239466947175955624516063835471869,   0.997779559634089374675625094823772087693}
    }  )
        u_IIR(clk, !rst_n, rd_ready_co, rd_data, filter_out);


endmodule
